1. Field of the Invention
The present invention generally relates to frequency comparators and clock regenerating devices using the same, and more particularly to a frequency comparator which compares digital signals and a clock regenerating device using such a frequency comparator.
2. Description of the Related Art
A clock reproduction device is known which uses a PLL (Phase-Locked Loop) and regenerates a clock from input data. In such a clock regenerating device, an output clock of the PLL is compared with a reference clock, and a voltage-controlled oscillator (VCO) provided in the PLL is controlled based on an error which corresponds to the difference between the output clock and the reference clock.
A clock regenerating device as described above is disclosed in U.S. Pat. No. 5,015,970. The clock regenerating device frequency-divides the output signal of the VCO at frequency-dividing ratios of 1/(N+1) and 1/(Nxe2x88x921). The two signals thus obtained are phase-compared with a reference clock obtained by frequency-dividing the output clock of the VCO at a frequency-dividing ratio of 1/M, so that a coarse adjustment signal can be obtained. The output clock of the VCO is also phase-compared with input data, and thus a fine adjustment is obtained. The coarse adjustment signal and the fine adjustment signals are added by a smoothing filter, and a resultant control signal which controls the VCO is obtained.
However, the above clock regenerating device has the following disadvantages. First, the device obtains the coarse adjustment signal by the phase comparing operation, and does not perform a frequency comparing operation independent of phases. Second, the device generates the VCO control signal which changes the phase of the output clock of the VCO on the basis of the coarse adjustment signal, and thus does not operate stably so that the PLL attempts to obtain a plurality of different in-phase (phase synchronized) states. If it is attempted to avoid unstable operation, there is nothing other than a modification in which the coarse adjustment is carried out more slowly. However, it takes a longer time to complete the coarse adjustment.
It is a general object of the present invention to provide a frequency comparator and a clock regenerating device using the same in which the above disadvantages are eliminated.
A more specific object of the present invention is to provide a frequency comparator capable of comparing frequencies independent of phases and generating a coarse adjustment signal by frequency comparison so that a stable and high-speed frequency pull-in operation can be carried out and to provide a clock reproduction device using such a frequency comparator.
The above objects of the present invention are achieved by a frequency comparator comprising: a circuit comparing, independently of a phase relationship between first and second clocks, frequencies of the first and second clocks and outputting first and second detection signals when the first clock has frequencies higher and lower than those of the second clock, respectively, the first and second detection signals being output for respective times based on a difference between the frequencies of the first and second clocks. Hence, it is possible to detect the frequency difference independently of the phase relationship between the first and second clocks and to thus obtain the first and second detection signals having pulse widths corresponding to the frequency difference.
The frequency comparator may be configured so that the circuit outputs the first detection signal when the frequency of the first clock is higher than that of the second clock at a first ratio or more, and outputs the second detection signal when the frequency of the first clock is lower than that of the second clock at a second ratio or more. Hence, it is possible to define an insensitive range in which none of the first and second detection signals are output when the first and second clocks have respective frequencies close to each other.
The frequency comparator may be configured so that the circuit comprises: a first counter which counts the first clock and outputs the first detection signal when a first count value of the first counter is equal to or greater than (n+a) where n and a are integers; a second counter which counts the second clock and outputs the second detection signal when a second count value of the second counter is equal to or greater than (n+b) where b is an integer; and a reset unit which resets the first and second counters when the first and second count values are both equal to or greater than the n. Hence, it is possible to detect the frequency difference independently of the phase relationship between the first and second clocks and to thus obtain the first and second detection signals having pulse widths corresponding to the frequency difference.
The frequency comparator may be configured so that one of the first and second detection signals is output until the reset unit resets the first and second counters.
The frequency comparator may be configured so that the circuit comprises: a first counter which counts the first clock and outputs the first detection signal when a first count value of the first counter is equal to or greater than (n+a) where n and a are integers; a second counter which counts the second clock and outputs the second detection signal when a second count value of the second counter is equal to or greater than (n+b) where b is an integer; a reset unit which generates a reset signal which resets the first and second counters when the first and second count values are both equal to or greater than the n; a first hold circuit which holds the first detection signal until the first hold circuit is reset in response to the reset signal; and a second hold circuit which holds the second detection signal until the second hold circuit is reset in response to the reset signal. Hence, it is sufficient that the first and second counters can count up to (n+a) and (n+b), respectively, so that the counters can be simplified.
The above objects of the present invention are also achieved by a clock regenerating device comprising: a frequency comparator comparing, independently of a phase relationship between first and second clocks, frequencies of the first and second clocks and outputting first and second detection signals when the first clock has frequencies higher and lower than those of the second clock, respectively, the first and second detection signals being output for respective times based on a difference between the frequencies of the first and second clocks; a phase comparator generating a fine-adjustment signal based on a difference between a phase of input data and a phase of the second clock; a combining unit generating a control signal from the first and second detection signals serving as a coarse-adjustment signal and the fine-adjustment signal; and an oscillator outputting a regenerated lock which is an oscillation output having a frequency based on the control signal and corresponds to the second clock. The combining unit combining the first and second signals and the fine-adjustment signal so that the following condition is satisfied:
(xcex94pf/xcex94ff) less than (xcex94pc/xcex94fc)
where xcex94pc and xcex94fc respectively denote a phase variation and a frequency variation in the regenerated clock caused by the coarse-adjustment signal per unit time, and xcex94pf and xcex94ff respectively denote a phase variation and a frequency variation in the regenerated clock caused by the fine-adjustment signal per unit time. Hence, it is possible to independently obtain frequency information from the second clock and phase information from the input data without any interference and to rapidly pull the circuit in phase.
The clock regenerating device may be configured so that the fine-adjustment signal includes fine-adjustment up and down signals based on the phase relationship between the input data and the second clock.
The clock regenerating device may be configured so that the coarse-adjustment signal is output during only a time based on the frequency difference between the first clock and the second clock.
The clock regenerating device may be configured so that the coarse-adjustment signal includes a voltage or current based on the frequency difference between the first clock and the second clock.
The clock regenerating device may be configured so that the frequency comparator comprises: a first counter which counts the first clock and outputs the first detection signal when a first count value of the first counter is equal to or greater than (n+a) where n and a are integers; a second counter which counts the second clock and outputs the second detection signal when a second count value of the second counter is equal to or greater than (n+b) where b is an integer; and a reset unit which resets the first and second counters when the first and second count values are both equal to or greater than the n.
The clock regenerating device may be configured so that the combining unit comprises an adder unit which adds an integrated value of the coarse-adjustment signal, an integrated value of the fine-adjustment signal, and an instantaneous value of the fine-adjustment signal. Hence, it is possible to integrate the coarse-adjustment and fine-adjustment signals by means of a common integrator and to completely eliminate the phase information from the second clock originally unnecessary in the in-phase pulling operation.
The clock regenerating device may be configured so that the combining unit comprises an adder unit which adds the coarse-adjustment signal and the fine-adjustment signal; an integral unit which integrates an output signal of the adder unit; an instantaneous voltage generating unit which generates an instantaneous voltage based on the fine-adjustment signal; and a mixing unit which adds an output of the integral unit and the instantaneous voltage and thus generates the control signal. Hence, it is possible to obtain the control signal based on both the frequency comparing operation and the phase comparing operation.
The clock regenerating device may be configured so that the adder unit comprises: a first current switch which charges a first capacitor provided in the integral unit with a constant current by a supply of the first detection signal; a second current switch which discharges the first capacitor with a constant current by a supply of the second detection signal; a third current switch which charges the first capacitor with a constant current by a supply of the first-adjustment signal; and a fourth current switch which discharges the first capacitor with a constant current by a supply of the fine-adjustment signal. Hence, it is possible to perform the integral operation by charging and discharging the first capacitor on the basis of the first and second detection signals and the fine-adjustment signal.
The clock regenerating device may be configured so that the adder unit comprises: a first OR circuit which performs an OR operation on the first detection signal and the fine-adjustment signal and thus outputs a first output; a second OR circuit which performs an OR operation on the second detection signal and the fine-adjustment signal and thus outputs a second output; a fifth switch which charges a first capacitor provided in the integral unit with a constant current by the first output; and a sixth switch which discharges the first capacitor with a constant current by the second output. Hence, it is possible to perform the integral operation by charging and discharging the first capacitor on the basis of the first and second detection signals and the fine-adjustment signal.
The clock regenerating device may be configured so that the mixing unit comprises: a buffer supplied with the output of the integral unit; and a first resistor supplied with an output of the buffer, the instantaneous voltage generating unit supplying a constant current to the first resistor in response to a supply of the fine-adjustment signal. Hence, the control signal can be obtained by adding the voltage generated by the constant current flowing in the first resistor in accordance with a supply of the fine-adjustment signal.
The clock regenerating device may be configured so that the instantaneous voltage generating unit comprises: a second resistor; a constant-voltage source which applies a constant voltage across the second resistor; and a unit which causes a current proportional to a current flowing in the second resistor to flow in the first resistor by a supply of the fine-adjustment signal. Hence, it is possible to stabilize the voltage drop developed across the first resistor by the current based on a supply of the fine-adjustment signal independent of variations in temperature, power supply and/or production process.
The clock regenerating device may be configured so that: the instantaneous voltage generating unit comprises an inverted amplifier having the first resistor as a feedback element; and the integral unit comprises another inverted amplifier having the first capacitor as a feedback element.
The clock regenerating device may be configured so that it further comprises a voltage dividing circuit which includes resistors connected in series and has an end fixed to a given potential, a divided voltage being supplied to the oscillator. Hence, it is possible to reduce the capacitance of the first capacitor and reduce the chip area occupied by the clock regenerating circuit.
The clock regenerating device may further comprise a phase-locked loop which is formed on a semiconductor chip on which the clock regenerating device is formed and which includes another integral unit which outputs said given potential. The two integral units are formed on the same chip and the first capacitor can further be reduced.
The clock regenerating device may be configured so that the oscillator comprises: a charge current switch supplying a charging current; a discharge current switch supplying a discharge current; a second capacitor which is charged and discharged by the charging and discharging currents, and a circuit part which generates a switching signal for turning ON one of the charge current switch and the discharge current switch by comparing a voltage developed across the second capacitor with first and second reference voltages and generating the regenerated clock from the switching signal, the charge current switch and the discharge current switch being coupled to the second capacitor through respective current output transistors. Hence, it is possible to suppress occurrence of noise caused by switching of the current charge and discharge switches.